IMPLEMENTATION OF MATRIX-VECTOR MULTIPLICATION ON FPGA USING SYSTOLIC ARCHITECTURE
The matrix -matrix and matrix-vector multiplications have numerous scientific computational applications like solving a linear system, designing image filters, neural network modelling, convolution, language recognition, etc. With increasing advancements of technology, the amount of data to be processed is also drastically increasing. Also the computation of matrix multiplication is time consuming if the order of the matrix is large. To perform the computation at a faster rate with lesser hardware and with high processing speeds, several architectures have been proposed. Of them, Systolic architecture is one such architecture. In this architecture, the system would contain a network of processing elements (PE) that periodically compute and pass the data through it. As this operation is analogous to flowing of blood through heart , this architecture is given the name 'systolic'. All the processing elements of systolic array are pipelined so that computation is done faster. In case of matrix-vector multiplication, each processing element has three delay elements and one MAC (Multiply and Accumulate) unit. Multiplication is done using array multiplier which uses CSA's , half adders and ripple carry adders. Outputs from the processing element will be the two inputs given to it and the output from MAC element after one clock cycle. The circuit is simulated using Xilinx Vivado software using Verilog as Hardware Description Language(HDL). This Systolic array architecture is widely incorporated by Google in its services like Google Translate, Google Search ,Google Photos etc where these services use Tensor processing units(TPUs) and systolic array is the heart of TPU. The main objective of the project is to reduce the computational time for matrix-vector multiplication using less hardware on FPGA.
Keywords: Pipelining, MAC unit,array multiplier , Verilog and Xilinx Vivado